VECTOR-LOGICAL FAULT SIMULATION
نویسندگان
چکیده
Context. The main idea is the creation of vector-logical in-memory computing (VLC), which uses only read-write transactions on address memory for faults-as-addresses simulation. There no traditional logic. VLC free from processor commands and ALU organization therefore focused implementation in SoC FPGA. A method deductive matrix synthesis transportation input faults, has a quadratic computational complexity, proposed. An inmemory simulator-automata vector-deductive simulation, based Objective. Development vector fault simulation primitive analysis logic circuits. Method. test set logical functionality are used. proposed development vectors’ algorithm truth table. intended verification tests using parallel combinations, over bits vectors memory. Results. matrices faults to output element, was Data structures have been developed digital circuits readwrite transaction memory, where combinations serve as address-columns. sequencer five blocks, that constitute vector-logic computing, connected with transactions, Verification models methods examples performed. Conclusions. scientific novelty consists following innovative solutions: 1) faults-as-addresses, first time; 2) an automata basis oriented FPGA LUT, embedded online simulator SoC, core RTL-level systems, 3) demonstration technological advantages performed numerous RTL-logic, accentuate manufacturability comparison analytical formulas during simulators construction; 4) vectors, vectorcolumns Boolean derivatives used construct minimal elements; 5) recursive formula permutation coordinates activity makes it possible significantly simplify obtaining practical significance lies fact will allow obtain speed real blocks at level hundreds nanoseconds. Complexity estimates corresponding algorithms given.
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ژورنال
عنوان ژورنال: Radio Electronics, Computer Science, Control
سال: 2023
ISSN: ['2313-688X', '1607-3274']
DOI: https://doi.org/10.15588/1607-3274-2023-2-5